A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N–1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.4 × 1.4 mm2 in a 0.18-μm CMOS process and consumes 52 mW. key words: spread spectrum clock generation, fractional phase-locked loop, delay-locked loop, phase compensation, fractional divider